A fly-back or switch-back voltage converter is a circuit to step up a voltage or to step down a voltage. For further illustration, FIG. 1 shows a circuit diagram of a typical fly-back voltage converter 10, which comprises a transformer 12 having a primary winding L1 coupled between an input voltage Vin and a switch M and a secondary winding L2 coupled between a capacitor Co and a controller chip 14. The controller chip 14 has an output pin EXT to provide a control signal S1 to switch the switch M, so as to transform a primary current Ip in the primary winding L1 into a secondary current Is in the secondary winding L2 to charge the capacitor Co to thereby produce an output voltage Vout, and a detection pin MCD coupled to the secondary winding L2 to detect the secondary current Is in order to control the off-time of the switch M. The converter 10 employs a control of constant on-time (regulated peak-current) and minimum-current detection. FIG. 2 is a waveform diagram to illustrate the control signal S1, primary current Ip and secondary current Is when the converter 10 ideally operates, in which waveform 20 represents the control signal S1, waveform 22 represents the primary current Ip, and waveform 24 represents the secondary current Is. Ideally, at the moment, for example time T2 in FIG. 2, that the primary current Ip in the primary winding L1 is switched off, the secondary current Is is immediately switched on in the secondary winding L2 to charge the capacitor Co. However, as shown in FIG. 3, noises 34 are actually introduced into the primary current Ip and secondary current Is when the primary current Ip and secondary current Is are switched on and off, because of the ringing effect of the primary current Ip and secondary current Is and the transferring delay resulted from the parasitic capacitor Cp between the primary winding L1 and secondary winding L2, and therefore error operations may occur in the converter 10. For an example, FIG. 4 shows a waveform diagram when noises induce error operations in the converter 10, in which waveform 40 represents the control signal S1, waveform 42 represents the primary current Ip, and waveform 44 represents the secondary current Is. After the primary current Ip is switched off and before the secondary current Is is switched on, noises 46 and 48 each completes a full waveform, causing the control circuit in the controller chip 14 to misjudge that the secondary current Is has charged the capacitor Co for a cycle, and therefore, the primary current Ip is switched on once more. Actually, the secondary current Is was not switched on and as a result, the primary current Ip will continuously increase, finally causing the transformer 14 to go into magnetic saturation and accordingly to fail to accomplish magnetic energy transformation.
To remove the noise interference, it has proposed to introduce a constant delay time (CDT) after the primary current Ip is switched off, as shown in FIG. 5, in which waveform 50 represents the control signal S1, waveform 52 represents the primary current Ip, waveform 54 represents the secondary current Is, and waveform 56 represents the CDT. With the insertion of the CDT before the switch-back current detector is enabled, the controller chip 14 is delayed for a time period CDT to detect the secondary current Is after the primary current Ip is switched off, and the interference of the noise 58 is prevented. However, it is hard for a circuit designer to determine a suitable CDT, since the duration of the noise 58 is sensitive to induced current, transformer size, parasitic capacitor and PCB layout.
Therefore, it is desired a control circuit and method for a fly-back voltage converter to avoid the noise interference without CDT technique.